Setting-up system for a television camera

ABSTRACT

A system for setting up a video camera. A signal processing circuit provides a plurality of signal channels which may be selectively connected to receive the camera output signal. A microcomputer is provided which stores digital correction values corresponding to minimum error values of distinct sub areas of the video signal. An error measuring circuit determines error values between the average value of a video signal taken over distinct sub areas of a television picture and a reference value. Each of the channels are selectively connected to the digital error measuring circuit to detect an error in the video signal passing through a connected channel.

BACKGROUND OF THE INVENTION

The invention relates to a setting-up system for a television camera.The system comprises a signal source incorporating a television pick-updevice for producing at least one video signal, a signal processingcircuit and a subsequent digital error measuring circuit fordetermining, in association with a microcomputer, error values betweenthe average value of a signal applied thereto taken over distinctsub-areas of a television picture, and a reference value. Themicrocomputer comprises at least one digital store having separate storelocations for storing digital correction values corresponding to minimalerror values and being associated with the sub-areas, and a signalcorrection circuit for effecting, while digital correction values areapplied, a signal correction resulting in a video signal corrected foreach sub-area.

Such a camera setting-up system is disclosed in U.S. Pat. No. 4,285,004.The Patent describes a camera, which is suitable for color televisionand comprises a pick-up device for producing three color signals.Corrections are effected to obtain a good registration of the threecolor pictures on display and to correct shading errors at black leveland peak white value. In addition, a gamma correction and a focusingcorrection can be effected. Depending on the type of the correction, thesignal correction circuit applies the correction signal to the pick-updevice (for scanning and focusing correction) or to a video signalprocessing circuit (for shading and gamma correction). To obtain thedifferent types of correction signals the error measuring circuitincorporates as many error measuring channels as there are types ofcorrection signals, and a reference channel, one of the three colorsignals being selectively applied to these error measuring channelsthrough a change-over switch.

SUMMARY OF THE INVENTION

The invention has for its object to provide a television camerasetting-up system in which corrections of a different type can beobtained with the least possible number of circuit components. Accordingto the invention, a setting-up system includes a signal processingcircuit which precedes the digital error measuring circuit whichincorporates a plurality of parallel channels each having a different,analog, signal transfer characteristic. The parallel channels areselectively connected through a change-over switch, to the digital errormeasuring circuit which incorporates a digital error measuring channelwhich is common to the parallel channels.

The invention recognizes that to obtain the simplest possibleconstruction of the setting-up system operating with the sub-areas, itis most advantageous to provide the digital error measuring circuit witha single, common digital error measuring channel and to process thesignal to be measured in such an analog manner in the relevant parallelchannel that the measured error value is characteristic of the type ofthe correction to be performed.

A setting-up system in accordance with the invention, suitable for acolor television camera, provides raster registration correction fortelevision line rasters, between a reference raster corresponding to areference signal and a raster corresponding to a camaera video signal,for which purpose a difference signal which represents the differencebetween the reference signal and the video signal is adjusted to aminimum. A parallel channel suitable for that purpose in the signalprocessing circuit has a transfer characteristic which is determined bya signal differentiating circuit which, during line scanning periods, isswitched-on by means of a switch provided therein and is switched offduring line blanking periods, and by a subsequent rectifier circuit.

In a further, practical embodiment the time constant of the signaldifferentiating circuit corresponds to a plurality of line periods.

To effect a further correction, a setting-up system in accordance withthe invention provides focusing correction. The parallel channelsuitable for that purpose in the signal processing circuit has atransfer characteristic which is determined by a high-pass filter and bya subsequent rectifier circuit.

In a further, practical embodiment the high-pass filter has a 12dB-per-octave-filter characteristic.

To effect another correction, a setting-up system in accordance with theinvention, suitable for a color television camera, provides a minimalpresence of a chrominance subcarrier wave in a luminance signal. Theparallel channel suitable for a measurement thereof incorporated in thesignal processing circuit, has a transfer characteristic which isdetermined by a bandpass filter tuned to the chrominance subcarrierfrequency and by a subsequent rectifier circuit.

To obtain an increased amount of measuring information, a setting-upsystem in accordance with the invention employs as the rectifier circuita full-wave rectifier circuit.

To effect a still further correction, a setting-up system in accordancewith the invention provides a measurement at a video signal level. Theparallel channel suitable for that purpose in the signal processingcircuit has a transfer characteristic which is determined by athreshold-limiter circuit.

In a further embodiment the threshold-limiter circuit comprises a pulsegenerator having an input to which the video signal to be measured isapplied and an output for supplying pulses when the instantaneous videosignal value has a certain offset from the selected level. The output isconnected to an input of an adder circuit having a further input towhich the video signal is applied and an output which is connected to aninput of a half-wave rectifier circuit. The output of the half waverectifier circuit for carrying a suppressed video signal during thepulses, is connected to the digital error measuring channel.

In a still further embodiment the pulse generator incorporates twovoltage comparison circuits, each having a first and a second output, afirst and a second input to which respective voltages to be compared areapplied and a third and a fourth input to which voltages may be appliedwhich block the voltage comparison circuit(s) between the first andsecond inputs and the first and second outputs, respectively. A first ora second input, respectively of each voltage comparison circuit iscoupled to said input of the pulse generator and the remaining inputs tothe microcomputer while the outputs of the voltage comparison circuitsare coupled to each other through diodes which are separately biased foreach voltage comparison circuit and coupled to the input of therectifier circuit through a further diode incorporated in the addercircuit.

DESCRIPTION OF THE DRAWING

The invention will now be further described by way of example accordancewith an embodiment of the invention described in accompanying drawing.

DESCRIPTION OF THE PREFERRED EMBODIMENT

In the drawing, a video signal source is denoted by VSS. The videosignal source VSS comprises a television pick-up device, not shown,which is suitable for black-white television or color television. Acomposite synchronizing signal SS1 is applied to an input terminal IT ofthe source VSS, this source producing one or more video signals intendedfor picture display, one of which is denoted by VS1. The video signalVS1 intended for picture display is applied to an analog signalprocessing circuit APC, an output of which is connected to an outputterminal OT. Correction signals CS1 and CS2 are respectively applied tothe source VSS and to the circuit APC from a signal correction circuitCC. The correction signal CS1 produces in, for example, a colortelevision pick-up device, a raster registration correction. Forblack-white and color television, the correction signal CS1 mightprovide an optical or electronic focusing correction at the pick-updevice incorporated in the source VSS. The correction signal CS2 mayproduce, for example, a shading correction or a gamma correction forblack-white or color television or a chrominance subcarrier suppressionin a luminance signal for color television. In the first instance, whichtype of correction is effected at the video signal source VSS and/or theanalog video signal processing circuit APC is not defined. Let it beassumed that after an optimum camera setting-up the circuit APC suppliesfrom the output terminal OT a video signal for optimum picture display.

For the supply of the correction signals CS1 and CS2 the correctioncircuit CC is connected to a data bus DB having, for example, 16 lines.Connected to the data bus DB are a microcomputer μC, a register REG anda digital signal processing circuit DPC. Other components connected tothe data bus DB are not shown. At the micro-computer μC it is shown thatit incorporates a timing signal generator TG1 and a memory M havingseparate memory locations m. Circuit DPC shows that a signal input isconnected to an output of an analog-to-digital converter A/D, a controlinput connected to an output of a timing signal generator TG2 and anenable input connected to an output of the register REG. A clock pulseinput of the converter A/D is connected to an output terminal of thetiming signal generator TG2. A signal input of the converter A/D isconnected to an output terminal OPT of a signal processing circuit PC inaccordance with the invention, which will be described hereinafter, andhas an input terminal IPT connected to an output of the signal sourceVSS carrying a signal VS2. For synchronizing purposes a synchronizingsignal SS2 is applied from the source VSS to the timing signal generatorTG2, which further supplies a line blanking signal HBS and, with colortelevision, a chrominance subcarrier burst gate signal BGS, outsidefield blanking, periods. The analog-to-digital converter A/D and thedigital signal processing circuit DPC form a digital error measuringchannel EMC which, in association with the microcomputer μC, ensuresthat the correct correction information is applied to the signalcorrection circuit CC through an error measuring circuit (A/D, DPC, TG2,REG). After setting-up, M correction values, each associated with acorresponding sub-area of a television picture, are stored in theseparate memory locations m of the digital memory M. With the describedconstruction, a memory M may be provided in the microcomputer μC foreach type of correction. For a detailed, possible construction of thecircuit DPC and a description of its operation in association with themicrocomputer μC reference is made to co-pending U.S. patent applicationSer. No. 449,075, filed Dec. 13, 1982. A possible construction of anoptimum linearly operating analog-to-digital converter A/D reference ismade to co-pending U.S. patent application Ser. No. 438,123, filed Nov.1, 1982.

For the present invention the detailed construction of the errormeasuring channel EMC and the cooperation with the microcomputer μC isof secondary importance. It is essential that there is one singledigital error measuring channel EMC which is connected to the outputterminal OPT of the signal processing circuit PC in accordance with theinvention.

The signal VS2 is applied to the input terminal IPT of the circuit PC.The signal VS2 may be a black-white or color television video signal.For color television, the signal VS2 may be a single color signal or aluminance signal, or a difference signal between two color signals. Thechoice of the type of the signal VS2 depends on the type of correctionto be effected during the setting-up. In accordance with one aspect ofthe invention, the circuit PC comprises a number of selective parallelchannels, designated PC1, PC2, PC3, PC4 and PC5, the channel selectionbeing associated with a specific, analog transfer characteristic and thesignal type selection of the signal VS2. The separate channels PC3, PC4and PC5 are followed by a common channel PC 345. Anticipating thedetailed description of the parallel channels PC1 to PC5, inclusive tobe selected, each having a specific, analog transfer characteristic, itis mentioned that, for a selected channel PC1, PC2, PC3 or PC5 thesignal VS2 is a video signal which varies between, for example, blacklevel and peak white value. The channel PC5 being chosen, the videosignal VS2 is a luminance signal for color television, as through thischannel, a chrominance subcarrier measurement is effected. It will beseen that a focusing correction for black-white or color television canbe effected through the channel PC3, it being possible to measureselectively through the channel PC2, the video signal above, below andbetween adjustable threshold values for effecting a gamma or shadingcorrection and it being possible to measure, through the channel PC1,the average video signal value for effecting, for example, a shadingcorrection. Channel PC4 being selected, the difference signal betweentwo color signals or between a color signal and a reference signal ismeasured for effecting a raster registration correction.

In the signal processing circuit PC, a common portion comprisingdifferential amplifiers A1, A2 and A3 precedes the parallel channels PC1to PC5, inclusive. The input terminal IPT is connected to the (+) inputof the amplifier A1 through a resistor R1. The output of the amplifierA1 is connected through resistor R2 to its (-) input and though aresistor R3 to the (-) input of the amplifier A2, the (+) input of whichis connected to ground through a resistor R4. The output of theamplifier A2 is connected through a resistor R5 to its (-) input andthrough a resistor R6 to a switch SC1. The switch SC1, and also otherswitches, are shown for the sake of simplicity as mechanical switches,but in reality it is an electronic switch. For a periodic switchingaction, a switching signal, such as, for example, the color subcarrierburst gate signal BGS, occurring for color television outside the fieldblanking periods, is applied to the switch SC1. Instead of the signalBGS, a different line periodic, pulse-shaped switching signal may beused having switching pulses on the television back porch in lineblanking periods. The resistor R6 is connected line-periodically, during(a portion of) the back porch in line blanking periods through theswitch SC1 to a terminal of a capacitor C1, another terminal of which isconnected to ground. The voltage-carrying terminal of the capacitor C1is connected to the (+) input of the amplifier A3, the (-) input ofwhich is connected to its output through a capacitor C2. The output ofthe amplifier A3 is connected to the (-) input of the amplifier A2through a resistor R7. The common portion of the signal processingcircuit PC preceding the parallel channels PC1 to PC5, respectively, isthus provided with a high-input impedance voltage follower (A1, R2) anda line-periodically active, keyed and feedback signal clamping circuitin which the amplifiers A2 and A3, the capacitors C1 and C2 and theswitch SC1 are incorporated. The amplifier A2 produces a signal VS3, apossible variation of which is shown in the drawing as a function of thetime. The signal VS3 is shown as a video signal having a linear,negatively-going variation during a line scan period between instants t1and t4, a black level located on the OV ground potential being presentin a preceding and a subsequent line blanking period. At the instant t4the, for example, peak white value is present, t2 and t3 denotingpreceding instants having less negative signal values -DC1 and -DC2.

The output of the amplifier A2 is connected to the parallel channels PC1to PC5, respectively. One of these parallel channels can always beconnected to the error measuring channel EMC, through switch S1, S2 orS345 and one of the further switches S3, S4 and S5. The switches S1, S2and S345, which together with S3, S4 and S5 form a change-over switch(S1, S2. S345, S3, S4, S5) are operated from the register REG, under thecontrol of the microcomputer μC. In addition, the register REG hasoutputs which are connected to inputs of a voltage source UV, which willbe shown to form part of the parallel channel PC2.

Terminals of the switches S1, S2 and S345 are interconnected andconnected to the (+) input of a differential amplifier A4 throughresistors R8. Resistors R9 and R10, respectively, connect the output ofthe amplifier A4 to its (-) input and to the output terminal OPT of thesignal processing circuit PC, respectively, which thus has a commonhigh-impedance voltage follower (A4, R9) at the output.

For the parallel channel PC1 which, in the drawing, is selected by wayof example, the (-) input of a differential amplifier A5 incorporatedtherein is connected to the output of the amplfier. A2 through aresistor R11. The (+) input of the amplifier A5 is connected to groundthrough a resistor R12 and its output is fed back to the (-) inputthrough a resistor R13. The output of the amplifier A5 is connected tothe (+) input of the voltage follower (A4, R9) through the closed switchS1 and the resistor R8. As a result of the described construction of theparallel channel PC1, this channel has a signal-inverting, lineartransfer characteristic so that the signal VS3 applied to it becomesavailable at the output terminal OPT in the inverted form and possiblyamplified, but non-processed in all further respects. When the digitalsignal processing circuit DPC has a construction as described in theabove-mentioned patent application, the average value of the (inverted)video signal VS3 is measured, more specifically always over seven lineportions of the line scanning periods, during a number of these linescanning periods. As a result thereof a television picture is dividedinto rows of seven sub-areas, the average value of the local videosignal being measured in each of these sub-areas. A comparison with areference value and an elimination of the difference by means ofcorrection values in the signal correction circuit CC (signal CS2)follows. When the applied video signal VS3 belongs to a uniformlyilluminated television pick-up circuit in the signal source VSS, thesetting-up by the parallel channel PC1 results in a shading correction.In the memory locations m of the memory M or in a corresponding memoryin the circuit CC, correction values are stored which, in the case of auniform illustration, results in the signal VS3 having a constant valueduring line scanning periods.

For the parallel channel PC2, it is shown that when, for example, theshown signal VS3 is applied to it, it applies a signal VS4 derivedtherefrom to the switch S2. From the shown signal VS4 it can be seenthat a threshold-limiter circuit is incorporated in the parallel channelPC2. A comparison of the signals VS3 and VS4 results in the parallelchannel PC2 allowing the applied signal to pass between two thresholdvalues -DC1 and -DC2 and that the parallel channel is blocked at lessnegative values (prior to the instant t2) and at more negative values(after the instant t3) during the line scanning period between theinstants t1 and t4. As a result thereof, the video signal contributionto the average value measurement in the error measuring channel EMC isonly effected at video signal values located between the values -DC1 and-DC2. If the said reference value corresponds to a predetermined,desired gamma of the video signal VS3, the elimination of the differencetherewith (correction signal CS2) results in the desired gamma beingachieved during this adjustment. Shifting the threshold values -DC1 and-DC2 and/or changing the difference between them results in a correctionwhich can be effected around every video signal level, in a desiredsignal amplitude band.

The drawing shows a parallel channel PC2 having the transfercharacteristic determined by the threshold-limiter circuit. In theconstruction shown there are, in addition to the describedthreshold-limiter circuit active between the values -DC1 and -DC2, twothreshold-limiter circuits which are active between the OV potential andthe value -DC1 and -DC2, respectively, and a threshold circuit which isactive at lower values than the value -DC2, it being assumed that alimited peak-white value (instant t4) is applied.

In the parallel channel PC2, the video signal VS3 supplied by theamplifier A2 is applied to an input T6 of a voltage comparator VC1 andto an input T3 of a voltage comparator VC2 through a resistor R14. Afurther input T7 of the voltage comparator VC1 is connected to an outputof the voltage source UV which produces an adjustable direct voltage-DC1 (the threshold value mentioned earlier in the signal VS3).Likewise, a further input T2 of the voltage comparator VC2 is connectedto the output of the voltage source UV, which output caries theadjustable direct voltage -DC2. The voltage comparators VC2 and VC1 eachhave two inversely related outputs designated T9, T10 and T11, T12,respectively. It is assumed that on the input T3 there is a voltagewhich is less negative than the voltage on the input T2, that is to saythe voltage at the input T3 is positive relative to the voltage at theinput T2. The output T9 carries a high positive voltage whichcorresponds to a logic 1 and that the output T10 carries a low positivevoltage which corresponds to the logic 0. The outputs T6 and T7 of thevoltage comparator VC1 corresponds to the respective inputs T2 and T3 ofthe comparator VC2, and the outputs T11 and T12 correspond to theoutputs T9 and T10. Put differently, the varying voltages between theinputs T2, T3 and T6, T7, respectively, are present in the inverted formas constant voltages between the outputs T9, T10 and T11, T12,respectively.

The outputs T9, T10, T11 amd T12, respectively, are connected to inputsof NAND-gates G1, G2, G3 and G4, respectively. A further input of eachgate G1, G2, G3 and G4 is connected to a further output of the voltagesource UV. The voltage comparator VC1 and the gates G3 and G4 form avoltage comparison circuit (VC1, G3, G4). The inputs of the gates G3 andG4 are connected to the voltage source UV forming inputs T5 and and T8of this voltage comparison circuit. The same holds for a voltagecomparison circuit (VC2, G1, G2) having inputs T1 and T4 which areconnected to the gates G1 and G2. The voltage comparison circuits (VC2,G1, G2) and (VC1, G3, G4) each having two outputs T13, T14 and T15, T16,respectively, connected to the gates incorporated therein, are availableas integrated circuits under the type designation NE 529 N of Signetics.

The voltage source UV supplies at the inputs T1, T4, T5 and T8, underthe control of data received from the register REG and so from themicrocomputer μC, combinations of a high positive voltage correspondingto a logic 1 and a low positive voltage corresponding to a logic 0. Thepredetermined combination determines, as will become apparenthereinafter, in conjunction with the threshold voltage values -DC1 onthe input T7 and -DC2 on the input T2, which portions of the videosignal VS3 applied to the inputs T3 and T6 are selected or suppressed inthe threshold-limiter circuit provided in the parallel channel PC2.Applying a logic 0 to a gate G1, G2, G3 or G4 through the respectiveinput T1, T4, T5 or T8 results in the path from the voltage comparatorinputs to the respective outputs T13, T14, T15 or T16 being blocked.

The outputs T13 and T14, respectively, of the circuit (VC2, G1, G2) areconnected to cathodes of diodes D1 and D2, respectively, whose anodesare interconnected at a junction point T17 and through a resistor R15 toa terminal which carries a voltage +U. The terminal carrying the voltage+U forms part of a voltage source, not shown, a further terminal ofwhich is connected to ground. The outputs T15 and T16, respectively ofthe comparator circuit (VC1, G3, G4) are connected to cathodes or diodesD3 and D4, respectively, the anodes of which are interconnected at ajunction T18 and connected through a resistor R16 to a terminal whichcarries the voltage +U. The anodes of the diodes D1, D2 and D3, D4,respectively, are connected to anodes of diodes D5 and D6, respectively,whose cathodes are interconnected at a junction T19. The diodes D1, D2and D5 are biased by the resistor R15, the diodes D3, D4 and D6 beingbiased by the resistor R16. At the junction T19 of the diodes D5 and D6,a signal PS is shown as a function of time t, such as is associated withthe previously described signal VS4. The signal PS is a pulse-shapedsignal which is supplied as an output signal by a pulse generator (UV;VC2, G1, G2, D1, D2, R15, D5; VC1, G3, G4, D3, D4, R16, D6) or, for thesake of brevity, pulse generator PG.

The junction T19 of the diodes D5 and D6, which junction forms theoutput of the pulse generator PG, is connected to the anode of the diodeD7. The cathode of the diode D7 is connected to a resistor R17 and to a(-) input of a differential amplifier A6. By means of its other terminalthe resistor R17 is connected to a coil L1, a further terminal of whichis connected to the output of the amplifier A2 by a resistor R18. Acenter tap of the coil L1 is connected to ground by a capacitor C3. Thediode D7 and the resistor R17 form an adder circuit (D7, R17) to whichthe video signal VS3 is applied through a delay circuit (L1, C3, R18).The delay circuit (L1, C3, R18) serves to compensate for the delayoccurring in the pulse-shaped signal PS relative to the video signalVS3. At the indicated instants t1, t2, t3 and t4, this delay isdisregarded for the sake of simplicity.

The adder circuit (D7, R17) has its output connected to the (-) input ofthe amplifier A6. The (+) input of the amplifieir A6 is connected toground through a resistor R19, the amplifier output being connectedthrough a diode D8 to the junction of a resistor R20, which is connectedto ground, and a resistor R21 connected back to the (-) input ofamplifier A6. The junction is connected to the terminal of the switchS2.

The amplifier A6, the diode D8 and the resistors R19, R20 and R21 form ahalf-wave rectifier circuit (A6, D8, R19, R20, R21) as only negativevoltages at the (-) amplifier input result in a positive voltage on thecathode of the diode D8. A positive voltage at the (-) input of theamplifier A6 results in a negative amplifier output voltage, the diodeD8 being non-conducting and the cathode thereof supplying the OV groundpotential. The rectifier circuit (A6, D8, R19, R20, R21) is theninoperative. Comparing the signals VS3, PS and VS4 shows that thepositively-going pulses in the signal PS added to the signal VS3 put therectifier circuit (A6, D8, R19, R20, R21) out of operation. The parallelchannel PC2 thus comprises a threshold-limiter circuit (PG, A6, D8).

Before it is explained how the signal selection at the signal VS3 bymeans of the voltage source UV having the threshold values -DC1 and -DC2is effected, further components present in the parallel channel PC2 willbe described. The cathodes of the diodes D5 and D6 which areinterconnected at the junction T19 are connected to the cathode of adiode D9. The anode of the diode D9 is connected to the cathode of adiode D10, whose anode is connected by a resistor R22 to an inputterminal TPT to which a test pattern signal is applied. The anode of thediode D10 is further connected to the anode of a diode D11 whose cathodeis connected to an output T0 of the voltage source UV. When the voltagesource UV supplies the ground potential or a negative, voltage on theoutput T0 and, for example, a positive voltage is applied to theterminal TPT, the diode D11 conducts and the diodes D9 and D10 arecutoff. The signal PS is applied without being disturbed to the junctionT19 through the diodes D5 and D6. If, however, it is desired that thepulse generator PG is switched off and to use for signal selection asignal which is to be applied externally to the terminal TPT, then thiscan be effected by adjusting the threshold values -DC1 and -DC2 to themaximum negative value and to supply an adequate positive voltage fromthe output T0. In this situation the diode D11 is non-conductive and thesignal applied to the terminal TPT through the connecting diode D10 andD9 may result in pulses in the signal PS at the junction T19, the diodesD5 and D6 being non-conducting. This selection feature can be utilizedwhen an electrically generated test pattern is used instead of anoptionally produced test pattern.

To explain the signal selection by means of the pulse generator PG thefollowing Table applies.

TABLE 1

The variation of the signal VS3 relative to the threshold values -DC1and -DC2 and the resulting logic values

    ______________________________________                                                  T3  T6      T9    T10    T11  T12                                   ______________________________________                                        0/VS3/-DC1  H     H       1   0      0    1                                   -DC1/VS3/-DC2                                                                             H     L       1   0      1    0                                   -DC2/VS3    L     L       0   1      1    0                                   ______________________________________                                    

wherein

H signifies a less negative voltage and

L a more negative voltage relative to the threshold value.

Table 2

Four selection codes and their results.

    __________________________________________________________________________    1           2           3           4                                         __________________________________________________________________________    T1 T4 T5 T8 T1 T4 T5 T8 T1 T4 T5 T8 T1 T4 T5 T8                               1  0  0  1  1  0  1  0  0  1  1  0  1  0  1  1                                T13                                                                              T14                                                                              T15                                                                              T16                                                                              T13                                                                              T14                                                                              T15                                                                              T16                                                                              T13                                                                              T14                                                                              T15                                                                              T16                                                                              T13                                                                              T14                                                                              T15                                                                              T16                              0  1  1  0  0  1  1  1  1  1  1  1  0  1  1  0                                0  1  1  1  0  1  0  1  1  1  0  1  0  1  0  1                                1  1  1  1  1  1  0  1  1  0  0  1  1  1  0  1                                T17   T18   T17   T18   T17   T18   T17   T18                                 0     0     0     1     1     1     0     0                                   0     1     0     0     1     0     0     0                                   1     1     1     0     0     0     1     0                                   T19         T19         T19         T19                                       0           1           1           0                                         1           0           1           0                                         1           1           0           1                                         __________________________________________________________________________

The biased diodes D1, D2 and D3, D4, respectively, correspond to a logicOR-function which also holds for the diodes D5 and D6.

From Table 2, which shows the selection codes and their results, itfollows that at the code 1 a positive pulse would occur in the signal PS(point T19) from the instant t2 to the instant t4. This results in therectifier circuit (A6, D8, R19, R20, R21) allowing the video signal VS3to pass only at signal values which are less negative than the thresholdvalue -DC1.

The code 2 results in two positive pulses, more specifically between theinstants t1 and t2, and t3 and t4. The shown signal PS correspondstherewith. Only video signal values located between the threshold values-DC1 and -DC2 are allowed to pass.

The code 3 would result in a positive pulse in the signal PS (point T19)between the instants t1 and t3. Now only video signal values are allowedto pass which are more negative than the threshold value -DC2.

The code 4 would result in a positive pulse in the signal PS (point T19)from the instant t3 onwards. All video signal values less negative thanthe threshold value -DC2 are then allowed to pass.

In addition to the described gamma correction during the setting-up, theparallel channel PC2 may further be utilized by means of the describedsignal selection for adjusting shading errors at specifically the blacklevel and the peak-white value. To this end an optical test pattern isused, having black and white blocks, for example in the form of a chessboard pattern. A uniform illumination of this test pattern and recordingthereof by the pick-up device in the signal sources VSS results in avideo signal VS2 which on display would show this black-white pattern.From the signal VS3 corresponding therewith, which signal is not shown,which has alternately the black-white information, it is only possiblewhen selection in accordance with code 1 (Table 2) is effected tomeasure the information at the black level. When selection is effectedin accordance with the code 3 (Table 2) only the information at thepeak-white values is measured. The code change-over from themicrocomputer μC is sufficient to perform these adjustments, without thenecessity of an adaptation for the shading measurement at the blacklevel in an optical path at the pick-up device in the source VSS.

When the test pattern with the black and white blocks is elaborated bygrey blocks, it is possible to adjust a desired gamma correction bymeans of a signal selection based on these grey blocks. These greyblocks may be provided, for example, around the center of the chessboard pattern.

The parallel channel PC3 is suitable for adjusting the optical andelectronic focusing, adjustment being made until a maximum ofhigh-frequency detail is obtained on display, by measuring ahigh-frequency component in the video signal VS3. The output of theampifier A2 carrying the video signal VS3 is connected to a terminal ofa resistor R23. The other terminal of the resistor R23 is connected to aground through a capacitor C4 arranged in series with a resistor R24.The junction between the capacitor C4 and the resistor R24 is connectedto ground by a capacitor C5 and a series resistor R25, the junctionbetween this capacitor C5 and series resistor R25 being connected to aterminal of the switch S3. The other terminal of the switch S3 andterminals of the switches S4 and S5 incorporated in the respectiveparallel channels PC4 and PC5 connected thereto are connected to aninput of a rectifier circuit RECT the output of which is connected to aterminal of the switch S345. The circuit RECT forms part of the parallelchannel PC 345 which is common to the parallel channels PC3, PC4 andPC5. The rectifier circuit RECT is in the form of a full-wave rectifiercircuit, whereby advantageously a measuring data increase is obtained atall three parallel channels PC3, PC4 and PC5 in association always withthe channel PC 345.

The transfer characteristic of the parallel channel PC3 is predominantlydetermined by a high-pass filter (C4, R24, C5, R25). In practice it hasbeen found that a 12 dB-per-octave filter characteristic is verysatisfactory for focus measurement. The following values may be chosenfor such a filter: capacitors C4 and C5 equal to 1.5 nF and resistorsR24 and R25 equal to 1000 Ohm. As there are also matching and isolatingresistors, not further described, the resistor R23 is a 75 Ohm matchingresistor. The analog transfer characteristic of the parallel channel(PC3, PC345) for the focusing adjustment is predominantly determined bythe high-pass filter (C4, R24, C5, R25) and the subsequent (full-waverectifier) circuit RECT.

The parallel channel (PC4, PC345) is intended for a raster registrationcorrection for which purpose the signal VS3 to be applied to it is adifference signal between two color signals or between a color signaland an (other) reference signal. The switches S4 and S345 are then inthe closed condition. The output signal VS3 of the amplifier A2 isapplied to a series arrangement of a capacitor C6, a resistor R27 and aswitch SC2 through a matching resistor R26. The junction of thecapacitor C6 and the resistor R27 is connected to a terminal of theswitch S4. The switch SC2 switches line periodically under the controlof the line blanking signal HBS, the switch SC2 being in the switched-oncondition during line scanning periods and in the switched-off conditionin line blanking periods. As a result thereof signal edges which mayoccur in the (video) line blanking periods do not affect the rasterregistration measurement. During the raster registration adjustment,adjustment is effected until a maximum measuring value has been obtainedas the reference value. The parallel channel PC4 then has a transfercharacteristic which is predominiently determined by a differentiatingcircuit (C6, R27, SC2). In practice it has been found that adifferentiating circuit is very satisfactory when the following valuesare chosen: Capacitor C6 equal to 0.22 μF and resistor R27 equal to 1000Ohm. The time constant of the differentiating circuit is equal to 220μs, which value is of the order of magnitude of some line periods (forexample a line period of 64 μs) and which has been found to be verysatisfactory in practice. A switch of the Philips type HEF 4066 B may bechosen for the switch SC2.

The parallel channel (PC5, PC345) is provided to enable a measurement ofthe degree to which the chrominance subcarrier is present in a luminancesignal VS3 applied thereto. To that end, the output of the amplifier A2is connected to an input of a bandpass filter F1 which is tuned to thechrominance subcarrier frequency. The construction of the filter F1 isnot further described and it may consist of two parallel-arrangedfilters, one tuned to the NTSC-chrominance sub-carrier frequency and theother one to the PAL-chrominance subcarrier frequency. The filter F1 isfollowed by, for example, a 20 dB-amplifier A7, the output of which isconnected to the switch S5. The transfer characteristic of the parallelchannel PC5 is here predominantly determined by the filtercharacteristic of the filter F1, the rectifier RECT contributing in thechannel (PC5, R345) to the transfer characteristic. The adjustment iseffected until a minimal measuring value has been obtained as thereference value.

From the preceding it appears that the parallel channels PC1, PC2 andPC3, PC4, PC5 in association with the channel PC345 each have aspecific, analog transfer characteristic which results in an error valueto be measured which is characteristic of the type of correction to beperformed. Summarizing the above, they are the conveyance of anon-processed signal for the shading correction (PC1), the signal levelselection (PC2) for gamma correction and shading correction at blacklevel and peak-white value, the high-frequency filter characteristic(PC3) for focusing, the signal differentiation (PC4) for the rasterregistration and the chrominance subcarrier filtering (PC5) for theminimalization thereof.

Instead of arranging the change-over switch (S1, S2, S345, S3, S4, S5)in the specified place, a change-over switch subsequent to the amplifierA2 and having five switching contacts for the respective parallelchannels PC1, PC2, PC3, PC4 and PC5 may be utilized.

Thus, there is described a system for setting up multiple parameters ofa television camera system. Those skilled in the art will recognize yetother embodiments described more particularly by the claims whichfollow.

What is claimed is:
 1. A system for establishing the parameters for atelevision camera which produces a video signal, comprising:a signalprocessing circuit including a plurality of parallel signal channels,each of said channels having a different signal transfer characteristic;a microcomputer having a memory with separate storage locations forstoring digital correction values corresponding to minimum error valuesof distinct sub areas of a television video signal; a digital errormeasuring circuit for determining error values between the average valueof a video signal taken over distinct sub areas of a television pictureand a reference value; a signal correction circuit for substituting saidstored digital correction values in said video signal; and means forselectively connecting each of said channels to said digital errormeasuring circuit, whereby an error in each of said channels may bedetected to indicate said stored correction values should be substitutedin said television video signal.
 2. A system as claimed in claim 1,suitable for a color television camera which determines a minimalpresence of a chrominance subcarrier in a luminance signal, one of saidparallel channels suitable for a measurement thereof having a transfercharacteristic which is determined by a bandpass filter tuned to thechrominance subcarrier frequency and by a subsequent rectifier circuit.3. A setting-up system as claimed in claim 2, wherein said rectifiercircuit is a full-wave rectifier circuit.
 4. A system according to claim1 wherein one of said channels is provided to effect raster registrationcorrections between a reference signal and a raster of said videosignal, said one channel including a signal differentiating circuitwhich during line scanning periods of said video signal is switched on,and during line blanking periods is switched off, and a rectifiercircuit connected to said differentiating circuit output.
 5. A system asclaimed in claim 4 wherein the time constant of the signaldifferentiating circuit corresponds to a plurality of line periods.
 6. Asystem as claimed in claim 4 wherein said rectifier circuit is afull-wave rectifier circuit.
 7. A system according to claim 1 whereinone of said channels performs a focusing correction, said channel havinga transfer characteristic determined by a high pass filter and asubsequent rectifier circuit.
 8. A system as claimed in claim 7, whereinthe high-pass filter has a 12 dB-per octave filter characteristic.
 9. Asetting-up system as claimed in claim 7, wherein said rectifier circuitis a full-wave rectifier circuit.
 10. A system according to claim 1wherein one of said parallel channels includes a limiter with athreshold level which is selectable, wherein specific signal levels maybe measured.
 11. A system as claimed in claim 10, wherein the limitercircuit comprises a pulse generator having an input to which the videosignal to be measured is applied, and an output for supplying pulseswhen the instantaneous video signal value has a certain offset from theselected level, the output being connected to an input of an errorcircuit having a further input to which the video signal is applied, andan output connected to an input of a half-wave rectifier circuit theoutput of which carries a suppressed video signal is connected to thedigital error measuring circuit.
 12. A setting-up system as claimed inclaim 11, wherein the pulse generator comprises two voltage comparisoncircuits each having a first and a second output, a first and secondinput to which respective voltages to be compared are applied, and athird and a fourth input to which voltages may be applied which blockthe voltage comparison circuit(s) between the first and second inputsand the first and second outputs, respectively, a first or a secondinput, respectively, of each voltage comparison circuit being coupled tosaid input of the pulse generator and the remaining inputs to themicrocomputer while the outputs of the voltage comparison circuits arecoupled to each other with diodes which are separately biased for eachvoltage comparison circuit and coupled to the input of the half-waverectifier circuit with a further diode.